1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a semiconductor input system such as Schmitt trigger circuits and the like used as input circuits and noise elimination circuits, for example.
2. Description of the Prior Art
Recently, the modern trend is toward the selection of low voltage level, low power consumption and high speed processing of semiconductor integrated circuits. Specifically, the enlargement of an available range of operational power source voltage and the increasing of a range of operational frequency for semiconductor integrated circuits are strongly required. In order to achieve those requirements, it must be required to increase performances of input circuits and internal logic circuits incorporated in semiconductor integrated circuits.
FIG. 29 is a circuit diagram showing a configuration of a conventional Schmitt trigger circuit (Hereinafter, it is also referred to as "the first conventional circuit".). This Schmitt trigger circuit has an inverter circuit 101 and is used as an input circuit and is placed in a semiconductor integrated circuit.
The inverter circuit 101 comprises P-MOS transistors 101a and 101b and N-MOS transistors 101c and 101d. These P-MOS transistors 101a and 101b and the N-MOS transistors 101c and 101d are connected in series between a high power source voltage VDD and a low power source voltage or a ground voltage VSS. In other words, the output terminal of the inverter circuit 101 is an intermediate point between the P-MOS transistors 101a, 101b and the N-MOS transistors 101c, 101d. The inverter circuit 101 receives an input signal Vin transferred from external devices (not shown) and converts it and then transmits the inverted input signal Vthc as an output signal from the inverter circuit 101 through the output node N2. In this explanation, the signal transferred from the intermediate node N1 is referred to as "the signal VBH" and the signal transferred from the intermediate node N3 is referred to as "the signal VBL".
The output signal Vthc is amplified by an amplifier circuit 102 comprising the inverter circuits 102a, 102b and 102c. The amplifier circuit 102 outputs an output signal Vout and a feed-back control signal VFB. The amplifier circuit 102 inverts and amplifies the output signal Vthc from the inverter circuit 101 as the preceding stage or the previous stage by the first stage inverter circuit 102a and then generates a signal Vthc1. The inverter circuits 102b and 102c connected in parallel in the following stage also inverts and amplifies the signal Vthc1 and then outputs the output signal Vout and the feed-back control signal VFB.
The output signal transferred from the inverter circuit 102c is transferred as an external output signal to external devices (not shown). The feed-back control signal transferred from the inverter circuit 102b to the gate terminal of the P-MOS transistor 103 connected between the node N1 in the inverter circuit 101 and the voltage ground source VSS and to the gate terminal of the N-MOS transistor 104 connected between the node N3 and the voltage power source VDD.
Since the P-MOS transistor 103 and the N-MOS transistor 104 are connected to the power source, VDD and VSS respectively, whose polarity is reversed to both the P-MOS transistor 103 and the N-MOS transistor 104, the hysteresis characteristics shown in FIG. 30 can be realized when the P-MOS transistor 103 and the N-MOS transistor 104 change conductive state. That is, the hysteresis characteristics of this circuit, as shown in FIG. 30, the hysteresis of the output voltage Vthc passes the path a and then passes the path b after the hysteresis reaches the point V1, when the voltage potential of the external input signal Vin is increased.
Next, when the voltage potential of the external input signal Vin is decreased, the hysteresis passes the path C and passes d after the hysteresis reaches the point V2. In this case, the range between the voltages V1 to V2 becomes the hysteresis range of this circuit.
In addition, the path e designated by the dotted line in FIG. 30 shows the usual input/output characteristics of the inverter circuit 101. In FIG. 30, the point P0 indicates the circuit threshold voltage, the point P1 designates the circuit threshold voltage of the inverter circuit 101 when the voltage Vthc is given to the path b. The point P1 designates the circuit threshold voltage of the inverter circuit 101 when the voltage Vthc passes the path b.
Next, the operation of the Schmitt trigger circuit shown in FIG. 29 will now be explained.
When the level of the external input signal Vin is in the VSS level, both the N-MOS circuits 101c and 101d are in a cut-off state, both the P-MOS transistors 101a and 101b are in an on-state. Both the potentials of the signals VBH and Vthc are in the voltage potential VDD, and both the potential of the output signal Vout and the feed-back control signal VFB are also in the VDD level.
In this state, the P-MOS transistor 103 and the N-MOS transistor 104 whose gates receive the feed-back control signal VFB are in the cut-off state and the on-state respectively (or a forward saturated state). The N-MOS transistor 104 enters a state which is equal to a state that diodes are connected to each other toward the forward bias referenced by the voltage power source VDD.
In the state that each circuit element is in the above state, when the potential of the external input voltage Vin transits to the VDD potential level from the VSS potential level, the P-MOS transistors 101a and 101b transit to the on-state and the N-MOS transistors 101c and 101d transit to the cut-off state. In addition, the P-MOS transistors 101a and 101b form a direct current path and changes the potential of the output signal Vthc from the inverter circuit section 101 to a desired voltage potential VSS level.
However, a current load in each of the N-MOS transistors 101c and 101d is increased because the N-MOS transistor 104 receiving the feed-back control signal VFB is in the state that it is connected between the voltage power source VDD and the intermediate node N3 in forward bias and a direct current path including the N-MOS transistor 104 is generated in addition to a direct current path formed by the P-MOS transistor 101a and 10b and the N-MOS transistors 101c and 101d.
The circuit threshold voltage of the inverter circuit section 101 is shifted toward the VDD level side (see the P1 side shown in FIG. 30) by the current load of this N-MOS transistor 104 so that the hysteresis characteristics is generated.
In addition, the direct current path is generating by the N-MOS transistor 104 until the N-MOS transistor 104 completely enters the cut-off state when the level of the feed-back control signal VFB is shifted over the circuit threshold voltage level of the inverter circuit 102a in the primary stage in the amplifier circuit 102 and then changed to the VSS voltage potential level.
The explanation described above shows the process that the external input signal Vin is changed from the VSS voltage level to the VSS voltage level. Conversely, in the primary state in which the VDD voltage level is changed to the VSS voltage level, the current load path is changed from the N-MOS transistor 104 to the P-MOS transistor 103 according to the state of the feed-back control voltage VFB, so that the voltage potential at each terminal is changed to the inverted state. Thereby, the threshold voltage level of the inverter circuit 101 is also shifted to the VSS level side (see P2 side shown in FIG. 30), so that the hysteresis characteristics is generated.
FIG. 31 is a circuit diagram showing a configuration of a conventional Schmitt trigger circuit having a stand-by function relating to the conventional Schmitt trigger circuit shown in FIG. 29. The components which are equal to the components used in the Schmitt trigger circuit shown in FIG. 29 in configuration and operation are used with the same reference numbers and the explanation for them are omitted here for brevity.
The Schmitt trigger circuit has the stand-by function by which a power consumption of the Schmitt trigger circuit becomes zero during a stand-by mode in addition to the function of the Schmitt trigger circuit shown in FIG. 29. In the conventional Schmitt trigger circuit shown in FIG. 31, a P-MOS transistor 111 and a N-MOS transistor 112 are placed in the direct current path in the inverter circuit section 101.
During the stand-by mode (STBY signal is in VSS level), the STBY signal is transferred to the gate of the N-MOS transistor 112, so that the N-MOS transistor 112 enters the cut-off state. Then, during the stand-by mode, the STBY signal is inverted by the inverter 113. The inverted STBY signal is transferred to the gate of the P-MOS transistor 111, so that the P-MOS transistor 112 enters the cut-off state. In addition, the P-MOS transistor 114 enters the ON-state, so that the level of the node N2 is fixed to the VDD voltage level.
A Schmitt trigger circuit having the following function is disclosed in the literature of the Japanese laid-open publication number:62-90021.
FIG. 32 is a diagram showing another conventional Schmitt trigger circuit (the second conventional Schmitt trigger circuit) disclosed in the above literature.
This second conventional Schmitt trigger circuit is incorporated as an input circuit in a semiconductor integrated circuit and the Schmitt trigger circuit has the inverter circuit sections 201 and 202.
In the inverter circuit section 201, the node N1 is used as the output terminal of the inverter circuit section 201, the P-MOS transistor 201a is connected between the voltage power source VDD and the output terminal N11, and the N-MOS transistor 201b is connected between the ground voltage power source VSS and the output terminal N11. In the inverter circuit section 202, the node N12 is used as the output terminal of the inverter circuit section 202, the P-MOS transistor 202a is connected between the voltage power source VDD and the output terminal N12, and the N-MOS transistor 202b is connected between the ground voltage power source VSS and the output terminal N12. An external input signal Vin is transferred to both the gates of the P-MOS transistors 201a, 202a and the N-MOS transistors 201b, 202b. The VBH signal is generated and transferred from the output terminal N11 and the VBL signal is transferred to the output terminal N12.
The inverter circuit sections 201 and 202 which receive commonly the external input signal are placed in parallel, the output terminal N11 of the inverter circuit section 201 is connected to the gate terminal of the P-MOS transistor 203a in the inverter circuit section 203 in the following stage, and the output terminal N12 of the inverter circuit 202 is connected to the gate terminal of the N-MOS transistor 203 in the inverter circuit section 203.
The inverter circuit section 203 having the output terminal N13 has the circuit configuration in which the P-MOS transistor 203a is connected between the voltage power source VDD and the output terminal N13 and the N-MOS transistor circuit 203b is connected between the ground voltage power source VSS and the output terminal N13. The output signal Vout transferred through the output terminal N13 to external devices is used as an external output signal.
When the circuit threshold voltages of the inverter circuit section 201 and the inverter circuit section 202 are Vt201 and Vt202, respectively, and when a transistor ratio W/L (hereinafter referred to as "W/L" for brevity, where W is a channel width, and L is a channel length) of the P-MOS transistor 201a is greater and when a transistor ratio W/L of the N-MOS transistor 201b is small in the inverter circuit section 201, the circuit threshold voltage of the inverter circuit section 201 against the external input signal Vin is shifted to the high voltage Vt201 side.
In contrast, in the inverter circuit section 202, when a transistor ratio W/L of the P-MOS transistor 202a is smaller and when a transistor ratio W/L of the N-MOS transistor 202b is larger in the inverter circuit section 202, the circuit threshold voltage of the inverter circuit section 202 against the external input signal Vin is shifted toward the low voltage Vt202 side.
Accordingly, this makes it possible to set the hysteresis characteristics shown in FIG. 33A based on the difference between the threshold voltages Vt201 and Vt202 when the circuit threshold voltages of the inverter circuit section 201 and 202 are set to the high voltage side threshold voltages Vt201 and the low voltage side threshold voltage Vt202, respectively.
However, in the conventional circuits (see FIG. 29 and FIG. 31), the circuit threshold voltage of the circuit section 101 is set to a desired voltage level by setting the following manners:
The feed-back control signal VFB as the output signal of the circuits is fed back to the circuits themselves, and the P-MOS transistor 103 and the N-MOS transistor 104 are set to an active state corresponding to each operation state and the current load is added to them in order to maintain the hysteresis characteristics, especially the hysteresis width.
By the increasing of the current load, there are drawbacks in the conventional Schmitt trigger circuits described above that a gain of the circuit is decreased, namely the amplifier ratio of the circuit becomes low and the peration frequency is decreased.
Furthermore, the channel conductance of the MOS transistors caused by the trend of decreasing the voltage potential level of the voltage power source VDD (the on-resistance of a MOS transistor is increased) and mutual conductance are decreased (a driving performance of a MOS transistor becomes low, namely a magnitude of the drain current flow is decreased.), so that the amplifier ratio of the conventional Schmitt trigger circuit becomes low and a delay of the output signal Vout is increased, thereby, it is difficult to guarantee the operation of the conventional Schmitt trigger circuit under a low voltage power source.
In addition, there is the following problem in both the second conventional circuit (see FIG. 32):
When the external input signal Vin is in the VSS voltage level, the P-MOS transistors 201a and 202a in the inverter circuits 201 and 202 enter the ON state, and the N-MOS transistors 201b and 202b enter the cut-off state, so that both the output signals VBH and VBL are VDD voltage level.
Furthermore, in the inverter circuit section 203, the P-MOS transistor 203a whose gate terminal receives the signals VBH and VBL transferred from the inverter circuits 201 and 202 in the previous stage enters the cut-off state. The voltage level of the output signal Vout from the output terminal N13 becomes the VSS voltage level because the N-MOS transistor 203b is in the on state.
In this state, when the external input signal Vin by which the threshold voltage of the low voltage potential circuit in the inverter circuit 202 will be changed is received, the level of the output signal VBL from the inverter circuit section 202 is changed from the VDD level to the VSS level, and thereby the N-MOS transistor circuit 203b enters completely the cut-off state during the transition state in which the level of the external input signal Vin is changed from the VSS level to the VDD level.
In the above state, the signals VBH and VBL which are transferred to the gate terminals of the P-MOS transistor 203a and the N-MOS transistor 203b in the inverter circuit section 203 become the VDD level and the VSS level, respectively, and both the P-MOS transistor 203a and the N-MOS transistor 203b enter the cut-off state.
Accordingly, because the output terminal N13 is not driven by the P-MOS transistor 203a and the N-MOS transistor 203b, the terminal N13 at which the output signal Vout appears has a high-impedance state. Thereby, there is a drawback that it is difficult to guarantee the circuit operation when the external input signal Vin in a low frequency range is received.
After this state described above, when the level of the external input signal Vin is over the circuit threshold voltage level Vt201 of the high voltage potential side in the inverter circuit 201, the signal VBH of the inverter circuit section 201 is inverted or shifted from the VDD level to the VSS level, the P-MOS transistor 203a in the inverter circuit 203 enters the on-state. As a result, the level of the output signal Vout from the output terminal N13 of the inverter circuit section 203 becomes the VDD level. Thereby, as shown in FIG. 33B, the input/output characteristics in which the output signal Vout transits through the path from the point "a" to the point "b" can be generated.
Since the explanation described above shows that the external input signal Vin transits from the VSS level to the VDD level, conversely, both levels of the output signals VBH and VBL become the VSS level in the initial state when the external input signal Vin transits from the VDD level to the VSS level, like the same manner in the explanation described above, the P-MOS transistor 203a whose gate terminal receives the signal VBH and the N-MOS transistor whose gate terminal receives the signal VBL enter the on-state and the N-MOS transistor 203b enters the cut-off state and the level of the output signal from the output terminal N13 is the VDD level.
In this state, when the external input signal Vin is changed from the VDD level to the VSS level during a transition state, the state at each terminal is the inverted state of the explanation described above, namely the level of each terminal transits the reverse voltage potential direction. Thereby, the output signal VBH of the inverter circuit section 201 is changed from the VSS level to the VDD level when the external input signal Vin whose voltage level is below that of the threshold voltage Vt201 of the high voltage side in the inverter circuit section 201, so that the P-MOS transistor 203a in the inverter circuit section 203 enters the cut-off state completely.
Therefore when the threshold voltage Vt201 of the high voltage potential level is shifted from the VDD level to the VSS level by the external input signal Vin, the state of the output terminal N13 of the inverter circuit section 203 assumes a high impedance state, and the output terminal N13 is not driven, so that it is difficult to guarantee the circuit operation when the external input signal Vin in a low frequency range is received.
After this, the N-MOS transistor 203b in the inverter circuit section 203 enters the on-state because the output signal VBL of the inverter circuit section 202 is changed from the VSS level to the VDD level when the level of the external input signal Vin is below the threshold voltage Vt202 level of the low voltage potential side in the inverter circuit section 202. As a result, the signal Vout output from the output terminal N13 of the inverter circuit section 203 becomes the VSS level, and then the input/output characteristics passing through the path from the point "c" to the point "d", as shown in FIG. 33B, is generated.
As described above in detail, in the process in which the level of the external input signal Vin is changed from the VSS level to the VDD level, the hysteresis characteristic is provided in which the signal Vout transits the path from the point "a" to the point "d", and the output signal Vout transits the path from the point "c" to the point "d" when the external input signal Vin is changed from the VDD level to the VSS level.
In addition, when the section from the threshold voltage Vt202 of the low voltage potential side to the threshold voltage Vt201 of the high voltage potential side is used as the hysteresis width and when the level of the external input signal Vin is changed from the VSS level to the VDD level or when the of the external input signal Vin is changed from the VDD level to the VSS level, the hysteresis characteristics can be obtained by keeping the external output voltage Vout corresponding to the voltage of the external input signal Vin immediately before this external input signal Vin enters the hysteresis range at a drain capacitance of the P-MOS transistor circuit 203a and the N-MOS transistor 203b in the inverter circuit section 203, at a wiring capacitance in which both the drains of the P-MOS transistor 203a and the N-MOS transistor 203b are connected to each other, and at the external load capacitance connected to the output terminal N13.
Accordingly, when the external input signal whose level is in the hysteresis range is transferred to the Schmitt trigger circuit, the output signal Vout from the Schmitt trigger circuit has the characteristics depended on a parasitic capacitance and an external load capacitance relating to the output terminal N13 in the inverter circuit section 203, so that there is a drawback that it is difficult to guarantee the circuit operation. In addition, as shown in FIG. 33C, when the amplitude of the external input signal Vin is in an input range of the external input signal Vin having an offset voltage at the VSS level and the VDD level sides, and when the voltage difference between the threshold voltage Vt202 at the low voltage side and the threshold voltage Vt201 at the high voltage side becomes smaller, it is difficult to drive the parasitic capacitance and the external load capacitance at the output terminal N13 to the VSS voltage level completely because a driving time period to drive the parasitic capacitance and the external load capacitance at the output terminal N13 in the inverter circuit section 203 becomes short.
Similarly, when the voltage difference between the threshold voltage Vt201 of the high voltage side and the offset voltage of the VDD level side in the inverter circuit section 203 becomes smaller, a driving time period to drive the parasitic load capacitance and the load capacitance at the output terminal N13 in the inverter circuit section 203 into the VDD level becomes short, so that it is difficult to drive these load capacitances at the output terminal N13 to the VDD voltage level and there is a drawback that a circuit response of the conventional Schmitt trigger circuit becomes unstable.
Furthermore, under the condition that a low voltage power source is used as the voltage power source VDD, the ratio of a circuit amplitude of the conventional Schmitt trigger circuit becomes low by reducing the channel conductance based on the Vgs (Vgs is the voltage between gate-source terminals) of the P-MOS transistor 203a and the N-MOS 203b transistor and by reducing the mutual conductance (decreasing the driving ability of the MOS transistor namely decreasing the amount of the drain current). Therefore there is a drawback in the prior art that it is difficult to guarantee stable circuit operation.
As described above in detail, there is the drawback that it is difficult to enlarge the voltage range in operation and to enlarge the frequency range in operation in the conventional semiconductor integrated circuits.